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29th May 2012, 09:39 AM
neeraj_m
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Pune University Electronics Enginering 3rd Sem-Digital Logic Design Exam – Download Previous Year’s Question Papers


There are two sections in the questions paper and the student is required to answer three questions from each section. The answers to each section must be written separately on separate booklets provided. The candidate must also draw detailed and neatly labeled diagrams as per the requirements of the question. The rules of the question paper also say that the candidate cannot answer two consecutive questions, thus, he/she must answer question 1 or 2, 3 or 4 and so on. The questions are mainly on designing according to the rules of digital logic. Some of the questions are the design of a Gray to BCD Converter using two dual 4:1 MUX IC’s and logic gates, designing an even parity generator using multiplexer and designing a pulse train generator. The second part of the question paper consists of descriptive questions such as advantages and disadvantages of a finite state machine, characteristics of memory devices and so on.


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3rd January 2014, 10:29 PM
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Default Re: Pune University Electronics Enginering 3rd Sem-Digital Logic Design Exam %u2013 Download Previous Year%u2019s Question Papers

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Pune University Computer Engineering 3rd Sem-Digital Electronics and Logic Design Exam – Download Previous Year’s Question Papers 1 21st April 2012 05:36 PM
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